In the beginning there was 8080
Here is the history of the x86 and links to documentation of specific version. Not sure about most of it really.
1st - 1978 - 8086
2nd - 1982 - 286
MMU and Protected mode.
3rd - 1985 - 386
32-bit instruction set and virtual mode.
4th - 1989 - 486
Integrated x87 FPU, pipelined processor and on-chip cache.
5th - 1993 - Pentium
Faster FPU and MMX.
6th - 1995 - Pentium Pro
7th - 2000 - Pentium 4 - 1.3 Ghz
8th - 2003 -
9th - 2008 -
10th - 2015 -
=== CPU Evolution
Fetch -> Decode -> Execute
Phase 1: Load instruction
Phase 2: Decode instruction / read register
Phase 3: Execute operation
Phase 4: Write back results
Pipelining (Fetch - Decode - Execute)
Allow mutiple instruction in flight at once
Instruction 1: Writes back
Instruction 2: Execute
Instruction 3: decode
Instruction 4: fetch
Problems: Branch delay and memory latency
Add large cache to lower memory latency
Slower then register
A cache miss takes time.
System that guess what memory is needed next.
Reads it into cache memory before needed
If guess wrong then useless work is performed.
Guess what code will run next and run it.