SRAM - Static random-access memory
SRAM uses a flip-flop to store each bit and common is six transistors each. SRAM loose the data when not powered but unlike DRAM it does not need to be refreshed.
Embedded SRAM - eSRAM
eSRAM is SRAM integrated on the same die as a microprocessor.
DRAM - Dynamic random-access memory
DRAM is created with one transistors and a capacitor per bit. So it takes up less space then SRAM. As the data is stored as an electronic charge in a capacitor it leaks away. So it needs to be refreshed at periodic intervals.
A cell is used to store one bit of data. It is often made up of one transistor and one capacitor. It is known as a 1T1C cell.
The cells are put in a rectangular grid. To store 16 bit's of data a grid can be 4x4 for example. The address to access our 16 bit memory cells would be 4 bits and the top two bits can be used to select the row and other two to select the column. Most DRAM now use multiplexed row and column address lines where the same address pins are first receive half the address and then the other half. So the 4 bit chip only need 2 pins for address.
To set the address to use one set the low part of it on the address pins and then latch it in with the Row Address Select (RAS). Then the same thing is used with the lower part and Column Address Select (CAS). In a asynchronous DRAM there are many fun rules with delays and signal times one must follow for it all to work. Reading or writing is done depending on the state of Write Enable (WE) and Output Enable (OE). Data is read from or written to the data pin (DQ). If everything works one has managed to set the value if a single bit.
As each cell only store one bit of data more then one matrix is used to store bytes. Put eight of them in parallel so each chip stores one bit of the final byte. All the chips get the same addresses and each chips output bit goes to a separate line on the data bus.
As each cell has a capacitor it leaks and sooner or later the data will be gone. So each cell needs to be refreshed from time to time.
GDDR SDRAM - Graphics Double data rate synchronous dynamic random-access memory
DDR SDRAM - Double data rate synchronous dynamic random-access memory - 2000
DDR use a clock and is driven on both the rising and falling edges on the clock signal. So it doubles the data bandwidth compared to SDRAM at the same clock frequency.
DDR4 - 2012
DDR3 - 2007
DDR2 - 2003
DDR1 - 2000
SDR SDRAM - Single Data Rate synchronous DRAM - 1998
BEDO DRAM - Burst EDO DRAM - 1994
BEDO can send out a sequence of data from the same row without any further address access to the memory. That way one can select a address and tell the memory to send out that data and three others pieces of data after it. It works as it only need to send out data for each sense amplifier.
EDO DRAM - Extended Data Out - 1994
EDO ram adds a latch on the output pin so the memory can hold the output longer. That way it can provide the data out even as the DRAM start the access of the next bit of data.
FPM DRAM - fast page mode DRAM - 1993
This was a change where if the Row part of a address was the same there was no need to latch on the RAS again. That allowed for faster subsequent access cycles to data on the same row.
PM DRAM - Page mode DRAM - 1992
VRAM - Video DRAM - 1986
VRAM is a variant of DRAM that has two ports for data. The first is used for normal DRAM access by the host computer. The second port is the read-only video port. The VRAM is used as a framebuffer and the graphic card use the VRAM port to read the frame buffer and send it to screen.
Embedded DRAM - eDRAM
eDRAM is DRAM integrated on the same die as a microprocessor.
DIMM - Dual in-line memory module - 1993
On a DIMM each pin has a seperate electical contact on each side. 72 to 288 pins variants.
SIMM - Single in-line memory module - 1982
A memory module with 30 pin (8 bit) or 72 pin (32 bits). FPM DRAM and EDO DRAM was used with SIMMs.
DIP - Dual in-line Package - 1979
A DIP package looks like the classical plastic IC spider like thing with legs.