SIMD

All in one, one for all

Single instruction, multiple data are instructions that perform the same operation one a set of data. The sets below is the sets that exist for x86. There was also 3DNow! but AMD killed it off in 2010 so let us speak of it no more. To learn what instruction sets are supported use CPUID at runtime.

AVX512 - 2015

- ZMM0-ZMM32

AVX2 - 2013

FMA - 2011

AVX - 2011

- Sixteen 256-bits YMM registers (YMM0-YMM16)

3D Vector Norma
- Flavors of SIMD - 2019
- Optimizing 4x4 matrix multiplication - 2017
- Modern SIMD Programming in the SSE Era - 2017
lization Using 256-Bit Intel® Advanced Vector Extensions (Intel® AVX)
- AVX Cloth - 2012
- SIMD at Insomniac Games (GDC 2015) - 2015

FC16 - 2009

SSE4.2 - 2008

- SSE: mind the gap! - 2016

SSE4.1 - 2007

SSSE3 - 2006

- Optimizing the Rendering Pipeline of Animated Models Using the Intel Streaming SIMD Extensions - 2009

SSE3 - 2004

- +13 instructions from SSE2
- Fast Skinning - 2005
- The Skeleton Assembly Line - 2005
- From Quaternion to Matrix and Back - 2005
- Slerping Clock Cycles - 2005

SSE2 - 2001

- Adds support for double precision and integer operations.
- For 64-bit mode adds eight registers (XMM8-XMM15)
- Very Fast, High-Precision SIMD/GPU Gradient Noise - 2012

SSE - 1999

- Streaming SIMD Extensions.
- 70 instructions
- Eight 128-bit registers XMM0-XMM7
- Single-precision floating-point operations (32-bit);
- Wyatt's World: Cracking Open the Pentium III - 1999

SSE (Streaming SIMD Extentions)
- SIMD architectures - 2000

MMX - 1996

- 57 SIMD instructions.
- Eight 64-bit registers MM0 - MM7.
- The registers are aliased on top of floating point registers FPR0-7.
- Only integer operations

Reference

Towards fearless SIMD - 2018

https://raphlinus.github.io/rust/simd/2018/10/19/fearless-simd.html